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? semiconductor components industries, llc, 2002 july, 2002 rev. 4 1 publication order number: mc10ep33/d mc10ep33, mc100ep33 3.3v / 5vecl 4 divider the mc10/100ep33 is an integrated 4 divider. the differential clock inputs. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the reset pin is asynchronous and is asserted on the rising edge. upon powerup, the internal flipflops will attain a random state; the reset allows for the synchronization of multiple ep33's in a system. the 100 series contains temperature compensation. ? 320 ps propagation delay ? maximum frequency > 4 ghz typical ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 5.5 v ? open input default state ? safety clamp on inputs ? q output will default low with inputs open or at v ee ? v bb output device package shipping ordering information mc10ep33d so8 98 units/rail mc10ep33dr2 so8 2500 tape & reel mc100ep33d so8 98 units/rail mc100ep33dr2 so8 2500 tape & reel mc10ep33dt tssop8 100 units/rail mc10ep33dtr2 tssop8 2500 tape & reel mc100ep33dt tssop8 100 units/rail mc100ep33dtr2 tssop8 2500 tape & reel l = wafer lot y = year w = work week *for additional information, see application note and8002/d h = mc10 k = mc100 a = assembly location so8 d suffix case 751 marking diagrams* tssop8 dt suffix case 948r alyw kep33 alyw hp33 hep33 alyw alyw kp33 1 8 1 8 1 8 1 8 1 8 1 8 http://onsemi.com
mc10ep33, mc100ep33 http://onsemi.com 2 1 2 3 45 6 7 8 q v ee v cc figure 1. 8lead pinout (top view) and logic diagram clk q clk v bb reset r 4 pin description pin clk*, clk * reset* ecl asynchronous reset function ecl clock inputs truth table clk x z clk x z reset z l q l f q h f z = low to high transition z = high to low transition f = divide by 4 function v bb reference voltage output q, q ecl data outputs v cc positive supply v ee negative supply * pins will default low when left open. figure 2. timing diagram clk reset q t rr attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor na esd protection human body model machine model charged device model > 4 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 91 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc10ep33, mc100ep33 http://onsemi.com 3 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input volta g e v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w jc thermal resistance (junction to case) std bd 8 tssop 41 to 44 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 18 26 34 18 26 34 18 26 34 ma v oh output high voltage (note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (single ended) 2090 2415 2155 2480 2215 2540 mv v il input low voltage (single ended) 1365 1690 1430 1755 1490 1815 mv v bb output voltage reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mv v ihcmr input high voltage common mode range (differential) (note 5) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 ohms to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep33, mc100ep33 http://onsemi.com 4 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 18 26 34 18 26 34 18 26 34 ma v oh output high voltage (note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (single ended) 3790 4115 3855 4180 3915 4240 mv v il input low voltage (single ended) 3065 3390 3130 3455 3190 3515 mv v bb output voltage reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mv v ihcmr input high voltage common mode range (differential) (note 8) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 7. all loading with 50 ohms to v cc 2.0 volts. 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 10ep dc characteristics, necl v cc = 0 v; v ee = 5.5 v to 3.0 v (note 9) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 18 26 34 18 26 34 18 26 34 ma v oh output high voltage (note 10) 1135 1010 885 1070 945 820 1010 885 760 mv v ol output low voltage (note 10) 1935 1810 1685 1870 1745 1620 1810 1685 1560 mv v ih input high voltage (single ended) 1210 885 1145 820 1085 760 mv v il input low voltage (single ended) 1935 1610 1870 1545 1810 1485 mv v bb output voltage reference 1510 1410 1310 1445 1345 1245 1385 1285 1185 mv v ihcmr input high voltage common mode range (differential) (note 11) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . 10. all loading with 50 ohms to v cc 2.0 volts. 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep33, mc100ep33 http://onsemi.com 5 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 12) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 23 28 33 24 30 36 25 31 37 ma v oh output high voltage (note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (single ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential) (note 14) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 13. all loading with 50 ohms to v cc 2.0 volts. 14. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 15) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 23 28 33 24 30 36 25 31 37 ma v oh output high voltage (note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (single ended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (single ended) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (differential) (note 17) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 16. all loading with 50 ohms to v cc 2.0 volts. 17. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep33, mc100ep33 http://onsemi.com 6 100ep dc characteristics, necl v cc = 0 v; v ee = 5.5 v to 3.0 v (note 18) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 23 28 33 24 30 36 25 31 37 ma v oh output high voltage (note 19) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 19) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (single ended) 1225 880 1225 880 1225 880 mv v il input low voltage (single ended) 1945 1625 1945 1625 1945 1625 mv v bb output voltage reference 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 20) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. input and output parameters vary 1:1 with v cc . 19. all loading with 50 ohms to v cc 2.0 volts. 20. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 21) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v opp output voltage amplitude (see figure 3) f in < 4.0 ghz f in < 4.5 ghz 700 600 700 600 700 600 mv t plh , t phl propagation delay to clk/q output differential reset/q 300 370 380 420 440 470 300 370 380 420 440 470 320 400 400 450 460 500 ps t rr set/rest recovery 150 100 200 100 200 100 ps t pw minimum pulse width reset 550 480 550 480 550 480 ps t jitter cycletocycle jitter 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (differential) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times q, q (20% 80%) 90 170 200 100 180 250 120 200 280 ps 21. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc 2.0 v.
mc10ep33, mc100ep33 http://onsemi.com 7 figure 3. input frequency (f in ) versus output voltage (v opp ) f in , input frequency (mhz) v opp , output voltage (mv) 5000 4000 3000 2000 1000 0 900 800 700 600 500 400 300 200 100 0 4500 3500 2500 1500 500 v tt = v cc 2.0 v figure 4. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc10ep33, mc100ep33 http://onsemi.com 8 package dimensions so8 d suffix plastic soic package case 75107 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751-01 thru 751-06 are obsolete. new standaard is 751-07 a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc10ep33, mc100ep33 http://onsemi.com 9 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop8 dt suffix plastic tssop package case 948r02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-.
mc10ep33, mc100ep33 http://onsemi.com 10 notes
mc10ep33, mc100ep33 http://onsemi.com 11 notes
mc10ep33, mc100ep33 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10ep33/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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